The present invention relates generally to parallel data alignment, and more particularly to synchronization of high speed parallel data transmissions.
The capabilities of information processing systems are constantly expanding. Such systems are increasingly called upon to process large amounts of information very quickly. The ability of information processing systems to act on information is dependent on the rate at which the system may receive information and the speed at which the system can process that information. In order to receive information more quickly, the systems are often provided information on parallel data lines. The information provided on the parallel data lines is generally associated together to form blocks of information. The use of parallel data lines allows a system to receive multiple pieces of information at any given moment.
A problem with parallel data lines is that transmission times across the data lines may vary, or skew, due to line lengths, process variations, aging, and environmental conditions. If the data transmission times are sufficiently different, then the information processing system may not group pieces of information received on the data lines in the proper format. The increased rate at which information processing systems process information also results in a decreased tolerance of variation in data transmission time. Thus, if information processing speeds increased by a factor of 10, such has occurred in the last several years, the allowable variation in transmission time decreases significantly.
Furthermore, information processing systems have increasingly been linked in ever greater computer networks, such as the Internet. The demand for information across these networks is tremendous, and has largely been met by ever increasing the rate in which information has passed between network nodes. For example, fiber optic transmission systems have increased data throughput such that data transmission rates have increased from 1.25 gigabits per second (Gb/s) to 2.5 Gb/s, 10 Gb/s, and are shortly expected to reach rates of 40 Gb/s. While specialized components may be able to receive data at such increased rates, the data rate is often slowed down for processing of the data by less specialized components. A common method of reducing a data rate is to deserialize, or put in parallel, received serial data. For example, serial data transmitted at 40 gigabits per second may be deserialized into a 16 bit bus operating at 2.5 gigahertz. At 2.5 Gb/s, however, skew tolerance for process variations and other factors is often minimal.